► DRAM TIMING Cor
DDR Memory Voltag APU DDR-PHY/PCIt-J FCH Voltage I APU-Core VoltagiAl APU-NB Voltage I
PHM Core Load Lim’ PWM NB Load Line Ccr/j
► BIOSTAR Memory Insig'i
► G.P.U Phase Control
f |*| method.
DRArt^freed will ^ SPDs. If Manual, sj|eed specified will programmed regardles If A